1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to an improved multi-chip package (MCP).
2. Description of the Related Art
Mobile applications require miniaturization of the various employed electronic components. Generally satisfactory miniaturization has been achieved through the development of submicron semiconductor fabrication technologies. However, continuous demand for ever increasing miniaturization has tested the limits of existing submicron technologies resulting in extended development periods and increased manufacturing costs. To address these limitations, a multi-chip package (MCP) technology has been employed, especially for mobile applications. A MCP refers to a composite chip product that allows a plurality of semiconductor chips, such as NOR flash memory chips, NAND flash memory chips, and SRAM chips, to be mounted in a single package. Generally, MCPs have a structure in which two or more semiconductor chips of the same kind are stacked. By employing MCP technology, an internal mounting area can be reduced by at least 50% and a line structure can be simplified, as compared to using a plurality of single-chip packages. Consequently, MCP technology may reduce the production cost, and increase the manufacturing productivity of mobile application devices.
Generally, each of the semiconductor chips mounted in an MCP includes a signal input unit for receiving a signal.
FIG. 1 is a diagram showing a signal input unit 10 provided on each of the semiconductor chips of a conventional MCP.
Referring to FIG. 1, the signal input unit 10 corresponds to a data input/output pad I/O PAD. The signal input unit 10 includes a receiver RX. The receiver RX includes a first (+) input terminal may be coupled with the data input/output pad I/O PAD to receive data DATA inputted through the data input/output pad I/O PAD, a second (−) input terminal receiving a reference voltage VREF, and an output terminal outputting internal data DATA_OUT obtained by amplifying a voltage difference between the data DATA and the reference voltage VREF.
The signal input unit 10 may further include a feedback unit CCOMP to compensate for a loading capacitance of the receiver RX. For reference, the feedback unit CCOMP is formed of a capacitor which is coupled between the output terminal and the first (+) input terminal of the receiver RX. The feedback unit CCOMP forms a positive feedback and provides a negative capacitance to the receiver RX.
However, the separate capacitor forming the feedback unit CCOMP of the signal input 10 may cause increases in the chip size and the input capacitance. Particularly, in an example of an MCP having a plurality of stacked semiconductor chips, the input capacitance may increase in proportion to the number of stacked semiconductor chips, thus negatively impacting the high-speed operation of the MCP.
Therefore, it would be desirable to be able to compensate for the loading capacitance of an MCP without increasing the overall circuit area of the MCP.